1. Field of the Invention
The present invention relates to the production of highly integrated circuits (CMOS) which contain p- and n-channel MOS transistors and gate electrodes consisting of double layers of metal silicides and polycrystalline silicon. The doping of the polycrystalline silicon layer is carried out by diffusion from the metal silicide layer.
2. Description of the Prior Art
Highly integrated circuits, wherein the gate electrodes consist of double layers of refractory metal silicides and polycrystalline silicon, and a process for their preparation, are disclosed, for example, in European Patent Application No. 0 163 871.
The continued increase in packing density and the resulting reduction in size of integrated circuits have added to the importance of short-channel effects in transistors. For example, such short-channel effects may be punch-through effects in the case of p-channel transistors or hot electron effects in the case of n-channel transistors. The doping conditions in the channel zone exert a substantial influence on the short-channel properties of the transistors.
Gate materials such as tantalum silicide or p.sup.+ -polycide which have a greater work function than n.sup.+ -polycide can be used to reduce the channel doping in the case of the n-channel transistor and the compensation in the channel zone in the case of the p-channel transistor while maintaining the threshold voltage. The term "polycide" refers to double layers consisting of a refractory metal silicide and polycrystalline silicon.
Short transistors having lengths of about 1 microns and good channel properties can be produced in this way. A lower compensation in the channel zone of the p-channel transistor reduces the punch-through effect due to the reduced space charge zone. The lower level of channel doping in the n-channel transistor reduces hot-electron such, for example, as the substrate current or the injection of charge carriers into the gate oxide and increases the mobility of the charge carriers. For further details of this effect, reference is invited to the article by Parrillo et al in the IEDM Tech. Digest, No. 15.6 (1984), pages 418 to 422. However, an impairment of the short channel properties occurs due to the lower level of channel doping.
In European Patent Application No. 0 135 163 there is disclosed a process for the production of highly integrated CMOS circuits wherein through the use of tantalum silicide as a gate material, a symmetrical threshold voltage of the n- and p-channel transistors having gate oxide thicknesses of about 20 nm amounting to approximately .+-.0.7 V can be obtained in a single, reduced channel implantation dose.
A further improvement in regard to the p-channel transistor can be obtained, as disclosed in the aforementioned European Patent Application No. 0 163 871 by the use of the n.sup.+ -polycide for the n-channel transistor and p.sup.+ -polycide for the p-channel transistor, involving no impairment of the n-channel transistor properties. Due to the difference of 1 V in the work function of the p.sup.+ -polycide as compared with the n.sup.+ -polycide, in the case of the p-channel transistor for gate oxide thicknesses of approximately 20 nm, the compensation of the channel zone can be entirely dispensed with so that the dependence of the threshold voltage upon the channel length becomes favorable similarly to that in the case of n-channel transistors with an n.sup.+ -polycide gate.
However, if both the short-channel properties of the p-channel transistor and the high breakdown voltage of the n-channel transistor are to be improved, and if the polysilicon/gate oxide boundary surface is to be retained, the use of p.sup.+ -polysilicon or p.sup.+ -polycide is advisable. However, under normal temperature loads in the CMOS process, p.sup.+ -polysilicon layers and p.sup.+ -polycide layers produced in accordace with known methods exhibit boron penetration effects unless expensive measures are taken, such, for example, as the use of nitrided gate oxide. Such a technique is described, for example, in an article by S. S. Wong et al in J. Electrochem. Soc. Vol. 130.5 (1983), pages 1139 to 1144.